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XRK39910 - 3.3V LOW SKEW PLL CLOCK DRIVER

Description

The XRK39910 is a high fanout phase locked-loop clock driver intended for high performance computing and data-communications applications.

It has eight zero delay LVTTL outputs.

When the OE pin is held low, all the outputs are synchronously enabled.

Features

  • Eight zero delay outputs 12mA balanced drive outputs Output frequency: 15MHz to 85MHz.

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Full PDF Text Transcription

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www.DataSheet4U.com JULY 2006 XRK39910 3.3V LOW SKEW PLL CLOCK DRIVER REV. 1.0.0 FUNCTIONAL DESCRIPTION The XRK39910 is a high fanout phase locked-loop clock driver intended for high performance computing and data-communications applications. It has eight zero delay LVTTL outputs. When the OE pin is held low, all the outputs are synchronously enabled. However, if OE is held high, all the outputs except Q2 and Q3 are synchronously disabled. Furthermore, when the PE is held high, all the outputs are synchronized with the positive edge of the CLKIN. When PE is held low, all the outputs are synchronized with the negative edge of CLKIN. The FB_IN signal is compared with the input CLKIN signal at the phase detector in order to drive the VCO.
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