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XRK32309 - LOW-COST 3.3V ZERO DELAY BUFFER

Description

FUNCTIONAL DESCRIPTION Offered in both 16 pin SOIC and TSSOP packages, XRK32309 is a low cost 3.3V zero delay buffer.

It is designed to distribute high speed clocks by taking one reference input and driving nine output clocks.

The feedback of its on-chip PLL is internally connected to the FB output.

Features

  • 10-MHz to 120-MHz operating range, compatible with CPU and PCI bus frequencies.
  • Zero input-output propagation delay.
  • Multiple low-skew outputs.
  • Output-output skew less than 250 ps Device-device skew less than 700 ps One input drives nine outputs, grouped as 4 + 4+1.
  • Less than 200 ps cycle-cycle jitter, compatible with.
  • Test Mode to bypass phase-locked loop (PLL) (see “Select Input Decoding” on page 2) Pentium®-based systems.

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Full PDF Text Transcription

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www.DataSheet4U.com MAY 2006 PRELIMINARY XRK32309 REV. P1.0.1 LOW-COST 3.3V ZERO DELAY BUFFER GENERAL DESCRIPTION FUNCTIONAL DESCRIPTION Offered in both 16 pin SOIC and TSSOP packages, XRK32309 is a low cost 3.3V zero delay buffer. It is designed to distribute high speed clocks by taking one reference input and driving nine output clocks. The feedback of its on-chip PLL is internally connected to the FB output. XRK32309 devices operate over 10-100 MHz frequency range with 30 pF loads and up to 120MHz with lower loads (10 pF). The -1H version has higher drive strength than the base -1 version, featuring faster rise and fall time. The XRK32309 has two banks each with four outputs.
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