Datasheet4U Logo Datasheet4U.com

XRK39351 - 9-OUTPUT PLL CLOCK DRIVER

Description

The XRK39351 is a low voltage PLL based clock driver designed for high speed clock distribution applications.

The XRK39351 has two reference clock inputs, one LVPECL and the other LVCMOS.

The REF_SEL input selects clock input to be used as the PLL’s reference source.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer

Other Datasheets by Exar (now MaxLinear)

Part Number Description
XRK39653 8-OUTPUT ZERO DELAY BUFFER
XRK39910 3.3V LOW SKEW PLL CLOCK DRIVER
XRK32308 3.3V ZERO DELAY BUFFER
XRK32309 LOW-COST 3.3V ZERO DELAY BUFFER
XRK32510 3.3V PHASE-LOCK LOOP CLOCK DRIVER

Full PDF Text Transcription

Click to expand full text
www.DataSheet4U.com xr FEBRUARY 2006 PRELIMINARY XRK39351 REV. P1.0.0 3.3V OR 2.5V, 9-OUTPUT PLL CLOCK DRIVER input is pulled low. This is a test mode intended for system debug purposes. The XRK39351 has an output/input frequency range of 25MHz to 200MHz with the PLL enabled and an input frequency range of 2MHz to 300MHz when the PLL is disabled (test mode). FEATURES GENERAL DESCRIPTION The XRK39351 is a low voltage PLL based clock driver designed for high speed clock distribution applications. The XRK39351 has two reference clock inputs, one LVPECL and the other LVCMOS. The REF_SEL input selects clock input to be used as the PLL’s reference source. The XRK39351 uses PLL technology to frequency lock its outputs to the clock reference input.
Published: |