Datasheet4U Logo Datasheet4U.com

XRK39653 - 8-OUTPUT ZERO DELAY BUFFER

Description

The XRK39653 is a low voltage high performance PLL based zero delay buffer/clock generator designed for high speed clock distribution applications.

It provides 9 low skew, low jitter outputs ideal for networking, computing and telecom applications.

Features

  • 8 LVCMOS Clock Outputs 1 Feedback Output LVPECL reference clock input 25-200 MHz input/output frequency range.
  • Input/Output range (÷4): 50-125MHz.
  • Input/Output range (÷8): 25-62.5MHz.
  • 150ps max output to output skew.
  • Two bypass test mode options.
  • Fully Integrated PLL 3.3V Operation Pin compatible with MPC9353 Industrial temp range: -40°C to +85°C 32-Lead TQFP Packaging FIGURE.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer

Other Datasheets by Exar (now MaxLinear)

Part Number Description
XRK39351 9-OUTPUT PLL CLOCK DRIVER
XRK39910 3.3V LOW SKEW PLL CLOCK DRIVER
XRK32308 3.3V ZERO DELAY BUFFER
XRK32309 LOW-COST 3.3V ZERO DELAY BUFFER
XRK32510 3.3V PHASE-LOCK LOOP CLOCK DRIVER

Full PDF Text Transcription

Click to expand full text
www.DataSheet4U.com xr FEBRUARY 2006 PRELIMINARY XRK39653 REV. P1.0.0 3.3V, 8-OUTPUT ZERO DELAY BUFFER use. The second is a full bypass mode that has the PLL and divider operation removed (BYPASS=0). In this mode the reference clock directly sources the outputs drivers. XRK39653 GENERAL DESCRIPTION The XRK39653 is a low voltage high performance PLL based zero delay buffer/clock generator designed for high speed clock distribution applications. It provides 9 low skew, low jitter outputs ideal for networking, computing and telecom applications. The PLL based design allows the 9 outputs (8 clock outputs and 1 feedback output) to be phase aligned to the input reference clock. The outputs source LVCMOS compatible levels and can drive 50Ω transmission lines.
Published: |