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ICS672-02 - QUADRACLOCK QUADRATURE DELAY BUFFER

Download the ICS672-02 datasheet PDF (ICS672-01 included). The manufacturer datasheet provides complete specifications, pinout details, electrical characteristics, and typical applications for quadraclock quadrature delay buffer.

Description

The ICS672-01/02 are zero delay buffers that generate four output clocks whose phases are spaced at 90° intervals.

Features

  • Packaged in 16-pin SOIC.
  • Pb (lead) free package, RoHS compliant.
  • Input clock range from 5 MHz to 150 MHz (depends on multiplier).
  • Clock outputs from up to 84 MHz (ICS672-01) and up to 135 MHz (ICS672-02).
  • Zero input-output delay.
  • Integrated x0.5, x1, x2, x3, x4, x5, or x6 selections.
  • Four accurate (.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (ICS672-01-Renesas.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

  • ICS670-01 - LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER (IDT)
  • ICS670-02 - LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER (IDT)
  • ICS670-03 - LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER (IDT)
  • ICS670-04 - LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER (IDT)
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Other Datasheets by Renesas
  • ICS672-01 - QUADRACLOCK QUADRATURE DELAY BUFFER
  • ICS670-01 - LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER
  • ICS670-03 - LOW PHASE NOISE ZERO-DELAY BUFFER/MULTIPLIER
  • ICS671-01 - ZERO DELAY LOW SKEW BUFFER/MULTIPLIER
  • ICS671-03 - LOW SKEW BUFFER
  • ICS674-01 - USER CONFIGURABLE DIVIDER
  • ICS601-01 - LOW PHASE NOISE CLOCK MULTIPLIER
  • ICS601-02 - LOW PHASE NOISE CLOCK MULTIPLIER

Full PDF Text Transcription

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QUADRACLOCK QUADRATURE DELAY BUFFER DATASHEET ICS672-01/02 Description The ICS672-01/02 are zero delay buffers that generate four output clocks whose phases are spaced at 90° intervals. Based on IDT’s proprietary low jitter Phase-Locked Loop (PLL) techniques, each device provides five low-skew outputs, with clock rates up to 84 MHz for the ICS672-01 and up to 135 MHz for the ICS672-02. By providing outputs delayed one quarter clock cycle, the device is useful for systems requiring early or late clocks. The ICS672-01/02 include multiplier selections of x0.5, x1, x2, x3, x4, x5, or x6. They also offer a mode to power-down all internal circuitry and tri-state the outputs. In normal operation, output clock FBCLK is tied to the FBIN pin.
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