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ICS673-01 - PLL BUILDING BLOCK

Description

The ICS673-01 is a low cost, high performance Phase Locked Loop (PLL) designed for clock synthesis and synchronization.

Included on the chip are the phase detector, charge pump, Voltage Controlled Oscillator (VCO), and two output buffers.

One output buffer is a divide by two of the other.

Features

  • Packaged in 16 pin SOIC (Pb-free, ROHS compliant).
  • Access to VCO input and feedback paths of PLL.
  • VCO operating range up to 120 MHz (5V).
  • Able to lock MHz range outputs to kHz range inputs through the use of external dividers.
  • Output Enable tri-states outputs.
  • Low skew output clocks.
  • Power Down turns off chip.
  • VCO predivide to feedback divider of 1 or 4.
  • 25 mA output drive capability at TTL levels.
  • Advance.

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Datasheet preview – ICS673-01

Datasheet Details

Part number ICS673-01
Manufacturer IDT
File Size 84.03 KB
Description PLL BUILDING BLOCK
Datasheet download datasheet ICS673-01 Datasheet
Additional preview pages of the ICS673-01 datasheet.

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Full PDF Text Transcription

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ICS673-01 PLL BUILDING BLOCK Description The ICS673-01 is a low cost, high performance Phase Locked Loop (PLL) designed for clock synthesis and synchronization. Included on the chip are the phase detector, charge pump, Voltage Controlled Oscillator (VCO), and two output buffers. One output buffer is a divide by two of the other. Through the use of external reference and VCO dividers (the ICS674-01), the user can customize the clock to lock to a wide variety of input frequencies. The ICS673-01 also has an output enable function that puts both outputs into a high-impedance state. The chip also has a power down feature which turns off the entire device. For applications that require low jitter or jitter attenuation, see the MK2069. For a smaller package, see the ICS663.
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