74F173 Datasheet - NXP

74F173 Quad D-type flip-flop 3-State

The 74F173 is a high speed 4 *bit parallel load register with clock enable control, 3 *state buffered outputs, and master reset (MR). When the two clock enable (E0 and E1) inputs are low, the data on the D inputs is loaded into the register simultaneously with low *to *hi.

74F173 Features

* Edge

* triggered D

* type register

* Gated clock enable for hold ”do nothing” mode

* 3

* state output buffers

* Gated output enable control

* Speed upgrade of N8T10 and current sink upgrade

* Controlled output edges to minimize gro

74F173 Datasheet (88.51 KB)