74F113 - Dual J-K negative edge-triggered flip-flops

Datasheet Details

Part number	74F113
Manufacturer	NXP
File Size	81.65 KB
Description	Dual J-K negative edge-triggered flip-flops
Datasheet	74F113_PhilipsSemiconductors.pdf

The 74F113, dual negative edge-triggered JK-type flip-flop,

individual J, K, clock (CP), set (SD) inputs, true and complementary outputs. The asynchronous SD input, when low, forces the outputs to the steady state levels as shown in the function table regardless of the level at the other inputs. A high level on the clock (CP) input enables the J and K inputs and data will be accepted. The logic levels at the J and K inputs may be allowed to change while the CP is high and flip-flop will perform according to the function table as long as minimum setup and.

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Published: Apr 3, 2005 |