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ZL30161 Network Synchronization Clock Translator

ZL30161 Description

ZL30161 Network Synchronization Clock Translator Short Form Data Sheet .
All device inputs and outputs are LVCMOS unless it is specifically stated to be differential.

ZL30161 Features

* Fully compliant SEC (G.813) and EEC (G.8262) flexible rate conversion digital phase locked loop (DPLL)
* Programmable DPLL/Numerically Controlled Oscillators (NCO)
* Synchronizes to any clock rate from 1 Hz to 750 MHz
* Three programmable synthesizers generate any c

ZL30161 Applications

* SyncE/SONET/SDH Timing Cards
* Synchronous Ethernet, 10 GBASE-R and 10 GBASE-W
* SONET/SDH, Fibre Channel, XAUI Osci Osco Ref0 Ref1 Ref2 Ref3 Ref4 Ref5 Ref6 Ref7 Ref8 Ref9 Ref10 Master Clock Diff / Single Ended Fr0= Br0
* Kr0
* Mr0/Nr0 Diff / Single Ended Fr1= Br1

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Network Synchronization Clock Translator Microsemi
Microsemi ZL30161-like datasheet