EDJ2108DEBG - 2G bits DDR3 SDRAM

Elpida Memory

Datasheet Details

Double-data-rate architecture: two data transfers per clock cycle.
The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture.
Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver.
DQS is edge-aligned with data for READs; centeraligned with data for WRITEs.
Differential clock inputs (CK and /CK).
DLL aligns DQ and DQS transitions with CK transi.

📁 EDJ2108DEBG Similar Datasheet

Other Datasheets by Elpida Memory

Published: Oct 17, 2014 |