EDJ4204EFBG - 1024M words x 4 bits 4G bits DDR3L SDRAM

Elpida Memory

Datasheet Details

Part number	EDJ4204EFBG
Manufacturer	Elpida Memory
File Size	392.78 KB
Description	1024M words x 4 bits 4G bits DDR3L SDRAM
Datasheet	EDJ4204EFBG-ElpidaMemory.pdf

Double-data-rate architecture: two data transfers per clock cycle.
The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture.
Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver.
DQS is edge-aligned with data for READs; centeraligned with data for WRITEs.
Differential clock inputs (CK and /CK).
DLL aligns DQ and DQS transitions with CK transi.

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Published: Jul 14, 2015 |