CY7C1276V18 Features
* Separate independent read and write data ports
* Supports concurrent transactions
* 300 MHz to 400 MHz clock for high bandwidth
* 4-Word Burst for reducing address bus frequency
* Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 800 MHz) at 40
CY7C1261V18-CypressSemiconductor.pdf
Datasheet Details
CY7C1276V18, CY7C1261V18
Cypress Semiconductor
404.82 KB
1.8v synchronous pipelined sram.
This datasheet PDF includes multiple part numbers: CY7C1276V18, CY7C1261V18.
Please refer to the document for exact specifications by model.
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CY7C1276V18 Distributor
