CY7C1270KV18 Features
* 36-Mbit density (2 M × 18, 1 M × 36)
* 550 MHz clock for high bandwidth
* Two-word burst for reducing address bus frequency
* Double data rate (DDR) interfaces (data transferred at 1100 MHz) at 550 MHz
* Available in 2.5 clock cycle latency
* Two input clocks (K and K) for
CY7C1268KV18-CypressSemiconductor.pdf
Datasheet Details
CY7C1270KV18, CY7C1268KV18
Cypress Semiconductor
622.44 KB
36-mbit ddr ii+ sram two-word burst architecture.
This datasheet PDF includes multiple part numbers: CY7C1270KV18, CY7C1268KV18.
Please refer to the document for exact specifications by model.
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CY7C1270KV18 Distributor
