CY7C1265XV18 Features
* Separate Independent Read and Write Data Ports
* Supports concurrent transactions
* 633 MHz Clock for High Bandwidth
* Four-word Burst for Reducing Address Bus Frequency
* Double Data Rate (DDR) Interfaces on both Read and Write Ports (data transferred at 1266 MHz) at 633 MHz
CY7C1263XV18-CypressSemiconductor.pdf
Datasheet Details
CY7C1265XV18, CY7C1263XV18
Cypress Semiconductor
1.17 MB
36-mbit qdr ii+ xtreme sram four-word burst architecture.
This datasheet PDF includes multiple part numbers: CY7C1265XV18, CY7C1263XV18.
Please refer to the document for exact specifications by model.
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CY7C1265XV18 Distributor
