CY7C1261V18 Datasheet - Cypress Semiconductor

CY7C1261V18 1.8V Synchronous Pipelined SRAM

CY7C1261V18 Features

* Separate independent read and write data ports

* Supports concurrent transactions

* 300 MHz to 400 MHz clock for high bandwidth

* 4-Word Burst for reducing address bus frequency

* Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 800 MHz) at 40

Datasheet Details

CY7C1261V18

Cypress Semiconductor

404.82 KB

1.8v synchronous pipelined sram.

📁 Related Datasheet

CY7C1262XV18 36-Mbit QDR II+ Xtreme SRAM Two-Word Burst Architecture (Cypress Semiconductor)

CY7C1263KV18 36-Mbit QDR II+ SRAM Four-Word Burst Architecture (Cypress Semiconductor)

CY7C1263V18 1.8V Synchronous Pipelined SRAM (Cypress Semiconductor)

CY7C1263XV18 36-Mbit QDR II+ Xtreme SRAM Four-Word Burst Architecture (Cypress Semiconductor)

CY7C1264XV18 36-Mbit QDR II+ Xtreme SRAM Two-Word Burst Architecture (Cypress Semiconductor)

CY7C1265KV18 36-Mbit QDR II+ SRAM Four-Word Burst Architecture (Cypress Semiconductor)

CY7C1265V18 1.8V Synchronous Pipelined SRAM (Cypress Semiconductor)

CY7C1265XV18 36-Mbit QDR II+ Xtreme SRAM Four-Word Burst Architecture (Cypress Semiconductor)

TAGS

CY7C1261V18 Distributor