CY7C1263XV18 Datasheet - Cypress Semiconductor

CY7C1263XV18 36-Mbit QDR II+ Xtreme SRAM Four-Word Burst Architecture

CY7C1263XV18 Features

* Separate Independent Read and Write Data Ports

* Supports concurrent transactions

* 633 MHz Clock for High Bandwidth

* Four-word Burst for Reducing Address Bus Frequency

* Double Data Rate (DDR) Interfaces on both Read and Write Ports (data transferred at 1266 MHz) at 633 MHz

Datasheet Details

CY7C1263XV18

Cypress Semiconductor

1.17 MB

36-mbit qdr ii+ xtreme sram four-word burst architecture.

📁 Related Datasheet

CY7C1263KV18 36-Mbit QDR II+ SRAM Four-Word Burst Architecture (Cypress Semiconductor)

CY7C1263V18 1.8V Synchronous Pipelined SRAM (Cypress Semiconductor)

CY7C1261V18 1.8V Synchronous Pipelined SRAM (Cypress Semiconductor)

CY7C1262XV18 36-Mbit QDR II+ Xtreme SRAM Two-Word Burst Architecture (Cypress Semiconductor)

CY7C1264XV18 36-Mbit QDR II+ Xtreme SRAM Two-Word Burst Architecture (Cypress Semiconductor)

CY7C1265KV18 36-Mbit QDR II+ SRAM Four-Word Burst Architecture (Cypress Semiconductor)

CY7C1265V18 1.8V Synchronous Pipelined SRAM (Cypress Semiconductor)

CY7C1265XV18 36-Mbit QDR II+ Xtreme SRAM Four-Word Burst Architecture (Cypress Semiconductor)

TAGS

CY7C1263XV18 Distributor