CY2SSTV16857 Datasheet (Cypress Semiconductor)

CY2SSTV16857, 14-Bit Registered Buffer

This 14-bit registered buffer is designed specifically for 2.3V to 2.7V VDD operation and is characterized for operation from 0°C to + 85°C.

All inputs are compatible with the JEDEC Standard for SSTL_2, except the LVCMOS reset (RESET) input.

All outputs are SSTL_2, Class II-compatible.

The SSTV16857

CY2SSTV16857 Features

* Differential Clock Inputs up to 280 MHz

* Supports LVTTL switching levels on the RESET pin

* Output drivers have controlled edge rates, so no external resistors are required

* Two KV ESD protection www.DataSheet4U.com

* Latch-up performance exceeds 100 mA: J