AS4C1M16E5 - 5V 1M x 16 CMOS DRAM

Alliance Semiconductor

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Datasheet Details

Part number	AS4C1M16E5
Manufacturer	Alliance Semiconductor
File Size	635.37 KB
Description	5V 1M x 16 CMOS DRAM
Datasheet	AS4C1M16E5_AllianceSemiconductor.pdf

AS4C1M16E5 Product details

Description

Address inputs Row address strobe Input/output Output enable Write enable Column address strobe, upper byte Column address strobe, lower byte Symbol tRAC tAA tCAC tOEA tRC tHPC ICC1 ICC5 -45 45 23 10 12 75 20 155 2.0 -50 50 25 12 13 80 20 145 2.0 -60 60 30 15 15 100 Unit ns ns ns ns ns mA mA Y $OOLDQFH 6HPLFRQGXFWRU w w w .D a at 135 2.0 Sh 25 t e e 4U ns .m o c 3 RI &RSULJKW $OOLDQFH 6HPLFRQGXFWRU $OO ULJKWV UHVHUYHG $6&0( )XQFWLRQDO GHVFU

Features

hyper page mode operation where read and write operations within a single row (or page) can be executed at very high speed by toggling column addresses within that row. Row and column addresses are alternately latched into input buffers using the falling edge of RAS and xCAS inputs, respectively. Also, RAS is used to make the column address latch transparent, enabling.

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Published: Mar 5, 2006 |