SN74SSQEB32882 Datasheet - Texas Instruments

SN74SSQEB32882 28-Bit to 56-Bit Registered Buffer

This JEDEC SSTE32882 28-bit 1:2 or 26-bit 1:2 and 4-bit 1:1 registering clock driver with parity is designed for operation on DDR3 registered DIMMs with VDD of 1.5 V, on DDR3L registered DIMMs with VDD of 1.35 V and on DDR3U registered DIMMs with VDD of 1.25 V. All inputs are 1.5 V, 1.35V and 1.25 V.

SN74SSQEB32882 Features

* 1

* 1-to-2 Register Outputs and 1-to-4 Clock Pair Outputs Support Stacked DDR3 RDIMMs

* CKE Powerdown Mode for Optimized System Power Consumption

* 1.5V/1.35V/1.25V Phase Lock Loop Clock Driver for Buffering One Differential Clock Pair (CK and CK) and Distributing to Four Dif

SN74SSQEB32882 Datasheet (724.38 KB)