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SN74SSQEB32882 Datasheet 28-Bit to 56-Bit Registered Buffer

Manufacturer: Texas Instruments

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General Description

This JEDEC SSTE32882 28-bit 1:2 or 26-bit 1:2 and 4-bit 1:1 registering clock driver with parity is designed for operation on DDR3 registered DIMMs with VDD of 1.5 V, on DDR3L registered DIMMs with VDD of 1.35 V and on DDR3U registered DIMMs with VDD of 1.25 V.

All inputs are 1.5 V, 1.35V and 1.25 V CMOS compatible.

All outputs are CMOS drivers optimized to drive DRAM signals on terminated traces in DDR3 RDIMM applications.

Overview

SN74SSQEB32882 www.ti.com SCAS896-PUB – JUNE 2010 28-Bit to 56-Bit Registered Buffer With Address Parity Test One Pair to Four Pair Differential Clock PLL Driver Check for Samples:.

Key Features

  • 1.
  • 1-to-2 Register Outputs and 1-to-4 Clock Pair Outputs Support Stacked DDR3 RDIMMs.
  • CKE Powerdown Mode for Optimized System Power Consumption.
  • 1.5V/1.35V/1.25V Phase Lock Loop Clock Driver for Buffering One Differential Clock Pair (CK and CK) and Distributing to Four Differential Outputs.
  • 1.5V/1.35V/1.25V CMOS Inputs.
  • Checks Parity on Command and Address (CS-Gated) Data Inputs.
  • Configurable Driver Strength.
  • Uses Internal Feedback.

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