SN74SSQEB32882 datasheet, buffer equivalent, Texas Instruments

Features and benefits

1
* 1-to-2 Register Outputs and 1-to-4 Clock Pair Outputs Support Stacked DDR3 RDIMMs
* CKE Powerdown Mode for Optimized System Power Consumption
* 1.5V/1.35V.

Application

* DDR3 Registered DIMMs up to DDR3-1866
* DDR3L Registered DIMMs up to DDR3L-1600
* DDR3U Registered DIMMs u.

Description

This JEDEC SSTE32882 28-bit 1:2 or 26-bit 1:2 and 4-bit 1:1 registering clock driver with parity is designed for operation on DDR3 registered DIMMs with VDD of 1.5 V, on DDR3L registered DIMMs with VDD of 1.35 V and on DDR3U registered DIMMs with VDD.

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