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SN74SSQE32882 - 28-BIT TO 56-BIT REGISTERED BUFFER

Datasheet Summary

Description

This JEDEC SSTE32882-compliant, 28-bit 1:2 or 26-bit 1:2 and 4-bit 1:1 registering clock driver with parity is designed for operation on DDR3 Registered DIMMs up to DDR3-1333 with VDD of 1.5 V.

All inputs are 1.5-V, CMOS-compatible.

Features

  • 1.
  • 2 JEDEC SSTE32882 Compliant.
  • 1-to-2 Register Outputs and 1-to-4 Clock Pair Outputs Support Stacked DDR3 DIMMs.
  • Chip Select Inputs Prevent Data Outputs from Changing State and Minimize System Power Consumption.
  • 1.5-V Phase Lock Loop Clock Driver Buffers One Differential Clock Pair (CK and CK) and Distributes to Four Differential Outputs.
  • 1.5-V CMOS Inputs.
  • Checks Parity on Command and Address (CS-gated) Data Inputs.
  • Supports LVCMOS.

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Datasheet preview – SN74SSQE32882

Datasheet Details

Part number SN74SSQE32882
Manufacturer Texas Instruments
File Size 831.58 KB
Description 28-BIT TO 56-BIT REGISTERED BUFFER
Datasheet download datasheet SN74SSQE32882 Datasheet
Additional preview pages of the SN74SSQE32882 datasheet.

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Full PDF Text Transcription

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SN74SSQE32882 www.ti.com ................................................................................................................................................. SCAS857A – MARCH 2008 – REVISED OCTOBER 2008 28-BIT TO 56-BIT REGISTERED BUFFER WITH ADDRESS PARITY TEST ONE PAIR TO FOUR PAIR DIFFERENTIAL CLOCK PLL DRIVER FEATURES 1 •2 JEDEC SSTE32882 Compliant • 1-to-2 Register Outputs and 1-to-4 Clock Pair Outputs Support Stacked DDR3 DIMMs • Chip Select Inputs Prevent Data Outputs from Changing State and Minimize System Power Consumption • 1.5-V Phase Lock Loop Clock Driver Buffers One Differential Clock Pair (CK and CK) and Distributes to Four Differential Outputs • 1.
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