CDC2586 driver equivalent, 3.3-v phase-lock-loop clock driver.
D Operates at 3.3-V VCC D Distributes One Clock Input to Twelve
Outputs
D Two Select Inputs Configure Up to Nine
Outputs.
The CDC2586 is a high-performance, low-skew, low-jitter clock driver. It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the clock output signals to the clock input (CLKIN) signal. It is specifically designed for use wit.
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