CDC2509C driver equivalent, 3.3-v phase-lock-loop clock driver.
D Distributes One Clock Input to One Bank of
Five and One Bank of Four Outputs
D Separate Output Enable for Each Output
.
The CDC2509C is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for.
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