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TH58NVG7D2GTA20 - 128 GBIT (8G x 8-BIT x 2) CMOS NAND E2PROM

Description

The TH58NVG7D2G is a single 3.3 V 128 Gbit (149,189,296,128 bits) NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as (8192 + 640) bytes  256 pages  8248 blocks.

Features

  • Organization Memory cell array Register Page size Block size TH58NVG7D2G 8832  512K  8  2 8832  8 8832 bytes (2M  160 K) bytes.
  • Modes Read, Reset, Auto Page Program, Auto Block Erase, Status Read, Page Copy, Multi Page Program, Multi Block Erase, Multi Page Copy, Multi Page Read.
  • Mode control Serial input/output Command control.
  • Number of valid blocks Min 7992 blocks Max 8248 blocks.
  • Power supply VCC  2.7 V to 3.6 V.
  • Access time Cell array to register.

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Full PDF Text Transcription

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TOSHIBA CONFIDENTIAL TH58NVG7D2GTA20 TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 128 GBIT (8G  8 BIT  2) CMOS NAND E2PROM (Multi-Level-Cell) DESCRIPTION The TH58NVG7D2G is a single 3.3 V 128 Gbit (149,189,296,128 bits) NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as (8192 + 640) bytes  256 pages  8248 blocks. The device has two 8832-byte static registers which allow program and read data to be transferred between the register and the memory cell array in 8832-byte increments. The Erase operation is implemented in a single block unit (2 Mbytes  160 Kbytes: 8832 bytes  256 pages). The TH58NVG7D2G is a serial-type memory device which utilizes the I/O pins for both address and data input/output as well as for command inputs.
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