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MT5C1009 Datasheet Preview

MT5C1009 Datasheet

128K x 8 SRAM

No Preview Available !

SRAM
MT5C1009
128K x 8 SRAM
WITH CHIP & OUTPUT ENABLE
AVAILABLE AS MILITARY
SPECIFICATIONS
•SMD 5962-89598
•MIL-STD-883
FEATURES
• Access Times: 12, 15, 20, 25, 35, 45, 55 and 70 ns
• Battery Backup: 2V data retention
• Low power standby
• High-performance, low-power CMOS process
• Single +5V (+10%) Power Supply
• Easy memory expansion with CE\ and OE\ options.
• All inputs and outputs are TTL compatible
OPTIONS
• Timing
12ns access
15ns access
20ns access
25ns access
35ns access
45ns access
55ns access
70ns access
MARKING
-12 (IT only)
-15
-20
-25
-35
-45
-55*
-70*
• Package(s)
Ceramic DIP (400 mil)
Ceramic DIP (600 mil)
Ceramic LCC
Ceramic LCC
Ceramic Flatpack
Ceramic SOJ
Ceramic SOJ
C
CW
EC
ECA
F
DCJ
SOJ
No. 111
No. 112
No. 207
No. 208
No. 303
No. 501
No. 507
• 2V data retention/low power L
*Electrical characteristics identical to those provided for the 45ns
access devices.
For more products and information
please visit our web site at
www.micross.com
PIN ASSIGNMENT
(Top View)
32-Pin DIP (C, CW)
32-Pin SOJ (SOJ)
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ1
DQ2
DQ3
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 VCC
31 A15
30 CNEC2
29 WE\
28 A13
27 A8
26 A9
25 A11
24 OE\
23 A10
22 CE\
21 DQ8
20 DQ7
19 DQ6
18 DQ5
17 DQ4
32-Pin Flat Pack (F)
32-Pin LCC (EC)
32-Pin SOJ (DCJ)
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ1
DQ2
DQ3
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 VCC
31 A15
30 NCEC2
29 WE\
28 A13
27 A8
26 A9
25 A11
24 OE\
23 A10
22 CE\
21 DQ8
20 DQ7
19 DQ6
18 DQ5
17 DQ4
32-Pin LCC (ECA)
NC 1
A16 2
A14 3
A12 4
A7 5
A6 6
A5 7
A4 8
A3 9
A2 10
A1 11
A0 12
DQ1 13
DQ2 14
DQ3 15
VSS 16
32 VCC
31 A15
30 NCEC2
29 WE\
28 A13
27 A8
26 A9
25 A11
24 OE\
23 A10
22 CE\
21 DQ8
20 DQ7
19 DQ6
18 DQ5
17 DQ4
4 3 2 1 32 31 30
A7
A6
A5
A4
A3
A2
A1
A0
DQ1
5
6
7
8
9
10
11
12
13
29 WE \
28 A13
27 A8
26 A9
25 A11
24 OE \
23 A10
22 CE1\
21 DQ8
14 15 16 17 18 19 20
GENERAL DESCRIPTION
The MT5C1009 is a 1,048,576-bit high-speed CMOS
static RAM organized as 131,072 words by 8 bits. This device
uses 8 common input and output lines and has an output en-
able pin which operate faster than address access times during
READ cycle.
For design exibility in high-speed memory applica-
tions, this device offers chip enable (CE\) and output enable
(OE\) features. These enhancements can place the outputs in
High-Z for additional exibility in system design.
Writing to these devices is accomplished when write
enable (WE\) and CE\ inputs are both LOW. Reading is ac-
complished when WE\ remains HIGH and CE\ and OE\ go
LOW. The devices offer a reduced power standby mode when
disabled, allowing system designs to achieve low standby power
requirements.
The “L” version offers a 2V data retention mode,
reducing current consumption to 2mW maximum.
All devices operate from a single +5V power supply
and all inputs and outputs are fully TTL compatible. It is par-
ticularly well suited for use in high-density, high-speed system
applications.
MT5C1009
Rev. 6.2 01/10
Micross Components reserves the right to change products or specications without notice.
1




Micross

MT5C1009 Datasheet Preview

MT5C1009 Datasheet

128K x 8 SRAM

No Preview Available !

SRAM
MT5C1009
FUNCTIONAL BLOCK DIAGRAM
VCC GND
A0
A1
A2
A3
A4
A5
262,144-BIT
MEMORY ARRAY
A6
A7
A12
COLUMN DECODER
A8 A9 A10 A11 A13 A14 A15 A16
POWER
DOWN
NOTE: The two least signicant row address bits (A8 and A6) are encoded using gray code.
DQ8
DQ1
CE\
OE\
WE\
TRUTH TABLE
CE\ WE\
HX
XX
LH
LH
LL
OE\
MODE
I/O PIN SUPPLY CURRENT
X Not Selected High-Z
ISBT2, ISBC2
X Not Selected High-Z
ISBT2, ISBC2
H Output Disable High-Z
ICC
L
Read
DOUT
ICC
X
Write
DIN
ICC
MT5C1009
Rev. 6.2 01/10
Micross Components reserves the right to change products or specications without notice.
2


Part Number MT5C1009
Description 128K x 8 SRAM
Maker Micross
PDF Download

MT5C1009 Datasheet PDF






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