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MT5C1005 Datasheet Preview

MT5C1005 Datasheet

256K x 4 SRAM

No Preview Available !

SRAM
FEATURES
• High speed: 12, 15, 17, 20, 25 and 35
• High-performance, low-power, CMOS double-metal
process
• Single +5V ±1O% power supply
• Easy memory expansion with CE and OE options
• All inputs and outputs are TTL-compatible
• Fast OE access time: 8ns
OPTIONS
• Timing
12ns access
15ns access
17ns access
20ns access
25ns access
35ns access
MARKING
-12
-15
-17
-20
-25
-35
• Packages
Plastic DIP (400 mil)
Plastic SOJ (400 mil)
Plastic SOJ (300 mil)
None
DJ
SJ
• 2V data retention
• 2V data retention, low power
L
LP
• Temperature
Commercial (O°C to +70°C)
Industrial (-40°C to +85°C)
Automotive (-40°C to +125°C)
Extended (-55°C to +125°C)
None
IT
AT
XT
• Part Number Example: MT5CI005DJ-25 IT
NOTE: Not all combinations of operating temperature, speed, data retention
and low power arenecessarilyavailable. Please contact the factory for availabil-
ity of specific part number combinations.
GENERAL DESCRIPTION
The MT5C1005 is organized as a 262,144 x 4 SRAM using
a four-transistor memory cell with a high-speed, low-power
CMOS process. MicronSRAMs are fabricated using double-
layer metal, double-layer polysilicontechnology.
For flexibility in high-speed memory applications,
Micron offers chip enable (CE) and output enable (OE) with
this organization. This enhancement can place the outputs
in High-Z for additional flexibility in system design.
256Kx 4 SRAM
WITH OUTPUT ENABLE
PIN ASSIGNMENT (Top View)
28-Pin DIP
(SA-5)
28-Pin SOJ
(SD-2)
(SD-3)
U1
o<
~
en
:D
:ls>:
A7 1 ~ 28 Vee
A8 2
27 A6
A9 3
26 A5
Al0 4
25 A4
All 5
24 A3
A12 6
23 A2
A13 7
22 Al
A14 8
21 AO
A15 9
20 NC
A16 10
19 D04
A17 11
18 D03
CE 12
BE 13
Vss 14
17 D02
16 DOl
15 WE
A7 1
A8 2
A9 3
Al0 4
All 5
A12 6
A13 7
A14 8
A1S 9
A16 10
A17 11
CE 12
BE 13
Vss 14
b28 Vee
P27 A6
P26 AS
P25 A4
P24 A3
P23 A2
P22 Al
P21 AO
P20 NC
P19 D04
P18 D03
17p D02
P16 DOl
P15 WE
Writing to this device is accomplished when write enable
(WE) and CE inputs are both LOW. Reading is accom-
plished when WE remains HIGH while output enable (OE)
and CE go LOW. The device offers a reduced power stand-
by mode when disabled. This allows system designers to
meet low standby power requirements.
The "L" and "LP" versions each provide a 70 percent
reduction in CMOS standby current (IsB2) over the standard
version. The LP version also provides a 90 percent reduc-
tion in TTL standby current (ISB1) through the use of gated
inputs on the WE, OE and address lines, which also facili-
tates the design ofbattery backed systems. That is, the gated
inputs simplify the design effort and circuitry required to
protect against inadvertent battery current drain during
power-down, when inputs may be at undefined levels.
All devices operate from a single +5V power supply and
all inputs and outputs are fully TIL-compatible.
MT5C10Q5
REV. 12/93
1-101
Micron Semiconductor, Inc., reserves the right to change products or specifications without notice.
©1993, Micron Semiconductor, Inc.




Micron

MT5C1005 Datasheet Preview

MT5C1005 Datasheet

256K x 4 SRAM

No Preview Available !

c.n
FUNCTIONAL BLOCK DIAGRAM
o< Vee GND
~
en
lJ
sl>:
AO-A17
aw:
oowCl
Cl
C/)
C/)
w
a:
Cl
«Cl
1,048,576-BIT
MEMORY ARRAY
oa---:l
I-
ooZ
~
D04
DOl
POWER
DOWN
OE
WE
MTSC1005
REV. 12f93
TRUTH TABLE
MODE
Of IT WE
DO
POWER
STANDBY
X H X HIGH-Z STANDBY
READ
L LH
Q
ACTIVE
NOT SELECTED H L H HIGH-Z ACTIVE
WRITE
XLL
D
ACTIVE
1-102
Micron Semiconductor, Inc., reS91V9S the right to change products or specifications without notice.
©1993, Micron Semiconductor, Inc.


Part Number MT5C1005
Description 256K x 4 SRAM
Maker Micron
PDF Download

MT5C1005 Datasheet PDF






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