MT5C1008 - 128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS

Datasheet Summary

Description

The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology.

Features

High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns Battery Backup: 2V data retention Low power standby High-performance, low-power CMOS process Single +5V (+10%) Power Supply Easy memory expansion with CE1, CE2, and OE options.
All inputs and outputs are TTL compatible 32-Pin LCC (ECA) 4 3 2 1 32 31 30 NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ1 DQ2 DQ3 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22.

ASI

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MT5C1008 128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS by ASI - Datasheet Preview — Datasheet preview – MT5C1008

Datasheet Details

Part number	MT5C1008
Manufacturer	ASI
File Size	187.16 KB
Description	128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS
Datasheet	MT5C1008 Datasheet
Additional preview pages of the MT5C1008 datasheet.

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Full PDF Text Transcription

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SRAM Austin Semiconductor, Inc.

Published: Aug 10, 2005 |