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MT5C1001 Datasheet Preview

MT5C1001 Datasheet

1 Meg x 1 SRAM

No Preview Available !

SRAM
FEATURES
• High speed: 12,15,17,20,25 and 35
• High-performance, low-power, CMOS double-metal
process
• Single +5V ±1O% power supply
• Easy memory expansion with CE option
• All inputs and outputs are TIL-compatible
OPTIONS
• Timing
12ns access
15ns access
17ns access
20ns access
25ns access
35ns access
MARKING
-12
-15
-17
-20
-25
-35
• Packages
Plastic DIP (400 mil)
Plastic SOJ (400 mil)
Plastic SOJ (300 mil)
None
DJ
SJ
• 2V data retention
• 2V data retention, low power
L
LP
• Temperature
Commercial (O°C to +70°C)
Industrial (-40°C to +85°C)
Automotive (-40°C to +125°C)
Extended (-55°C to +125°C)
None
IT
AT
XT
• Part Number Example: MT5C1001DJ-20 IT
NOTE: Not all combinations of operating temperature, speed, data retention
and low power are necessarily available. Please contact the factory for availabil-
ity of specific part number combinations.
GENERAL DESCRIPTION
The MT5C1001 is organized as a 1,048,576 x 1 SRAM
using a four-transistor memory cell with a high-speed,
low-power CMOS process. Micron SRAMs are fabricated
using double-layer metal, double-layer polysilicon
technology.
For flexibility in high-speed memory applications,
Micron offers chip enable (CE) capability. This enhance-
ment can place the outputs in High-Z for additional
flexibility in system design. The xl configuration features
separate data input and output.
1 MEGx 1 SRAM
PIN ASSIGNMENT (Top View)
28-Pin DIP
(8A-5)
28-Pin SOJ
(8D-2)
(8D-3)
CJ1
o<
!:i
en
:IJ
ls>:
Al0 1 '-J
All 2
A12 3
A13 4
A14 5
A15 6
NC 7
A16 8
A17 9
A18 10
A19 11
Q 12
WE 13
VSS 14
28 Vee
27 A9
26 AS
25 A7
24 A6
23 AS
22 A4
21 NC
20 A3
19 A2
18 A1
17 AO
16 D
15 CE
Al0 [ 1
All [ 2
A12 [ 3
A13 [ 4
A14 [ 5
A15 6
NC l 7
A16 [ 8
A17 [ 9
A18 [ 10
A19 [ 11
w~
~
12
13
Vss [ 14
28 b Vee
P27 A9
P26 A8
25 A7
24 A6
23 A5
22 A4
P21 NC
20
19
PpAA23
18 pAl
P17 AO
~ ~E16
15
Writing to this device is accomplished when write enable
(WE) and CE inputs are both LOW. Reading is accom-
plished when WE remains HIGH while CE goes LOW. The
device offers a reduced power standby mode when dis-
abled. This allows system designers to meet low standby
power requirements.
The "L" and "LP" versions each provide a 70 percent
reduction in CMOS standby current (ISB2) over the standard
version. The LP version also provides a 90 percent reduc-
tion in TIL standby current (ISBl) through the use of gated
inputs on the WE and address lines, which also facilitates
the design of battery backed systems. That is, the gated
inputs simplify the design effort and circuitry required to
protect against inadvertent battery current drain during
power-down, when inputs may be at undefined levels.
All devices operate from a single +5V power supply and
all inputs and outputs are fully TIL-compatible.
MT5C1001
REV. 12193
1-31
Micron Semiconductor, Inc., reserves the right to change products or specifications without notice.
©1993, Micron Semiconductor, Inc.




Micron

MT5C1001 Datasheet Preview

MT5C1001 Datasheet

1 Meg x 1 SRAM

No Preview Available !

(II
o<
~
en
»:s:D:
AO-A19
ewx:
oQ
()
w
Q
eeewxnn:
Q
«Q
FUNCTIONAL BLOCK DIAGRAM
Vee GND
1,048,576-BIT
MEMORY ARRAY
1----< 1----- D
I---~ > - - - - Q
o-exI:
oIz-
()
~
POWER
DOWN
TRUTH TABLE
MODE
STANDBY
READ
WRITE
CE WE
INPUT
H X DON'T CARE
L H DON'T CARE
LL
DATA-IN
OUTPUT
HIGH-Z
Q
HIGH-Z
POWER
STANDBY
ACTIVE
ACTIVE
MT5C1001
AEV.12193
1-32
Micron Semiconductor, Inc., reserves the right to change products or specifications without notice.
@1993,MicronSemiconductor,lnc.


Part Number MT5C1001
Description 1 Meg x 1 SRAM
Maker Micron
Total Page 10 Pages
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