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MT5C1008 Datasheet Preview

MT5C1008 Datasheet

128K x 8 SRAM

No Preview Available !

SRAM
FEATURES
• High speed: 12, 15, 17,20,25 and 35ns
• High-perfonnance, low-power, CMOS double-metal
process
• Single +5V ±10% power supply
• Easy memory expansion with CEl, CE2 and OE
options
• All inputs and outputs are TIL-compatible
• Fast OE access time: 8ns
OPTIONS
• Timing
12ns access
15ns access
17ns access
20ns access
25ns access
35ns access
MARKING
-12
-15
-17
-20
-25
-35
• Packages
Plastic DIP (400 mil)
Plastic SOJ (400 mil)
Plastic SOJ (300 mil)
• 2V data retention
• 2V data retention, low power
None
DJ
SJ
L
LP
• Temperature
Commercial (O°C to +70°C)
Industrial (-40°C to +85°C)
Automotive (-40°C to +125°C)
Extended (-55°C to +125°C)
None
IT
AT
XT
• Part Number Example: MT5C1008DJ-25 LP
NOTE: Not all combinations of operating temperature, speed, data retention
and low power are necessarily available. Pleasecontact the factory for availabil-
ity of specific part number combinations.
GENERAL DESCRIPTION
The MT5ClO08 is organized as a 131,072 x 8 SRAM using
a four-transistor memory cell with a high-speed, low-power
CMOS process. Micron SRAMs are fabricated using double-
layer metal, double-layer polysilicon technology.
For flexibility in high-speed memory applications,
Micron offers dual chip enables (CEl, CE2) and an output
enable (OE). This enhancement can place the outputs in
High-Z for additional flexibility in system design.
128Kx 8 SRAM
WITH OUTPUT ENABLE
PIN ASSIGNMENT (Top View)
32-Pin DIP
(SA-6)
NG 1 ~ 32 Vee
Al. 31 A15
Al'
A12
A7
30 GE2
29 WE
28 A13
A6 27 AS
A5 7
26 AS
A. 25 A11
A3 2. 6E
A2 10
23 Al0
Al 11
22 GEl
AO 12
21 008
DQl 13
20 007
DQ2 14
19 DQ6
DQ3 15
18 005
V" 16
17 DQ4
32-Pin SOJ
(SD-4, SD-5)
NG
A16
A14
A12
A7
A6
A5
A4
A3
A2
Al
AD
DQl
002
OQ3
Vss
1
2
3
4
5
6
9
10
11
12
13
14
15
16
32 Vee
31 A15
30 GE2
29 WE
28 A13
27 A8
26 AS
25 A11
24 OE
23 Al0
22 GEl
21 DOS
20 DQ7
19 006
18 DOS
17 OQ4
C1I
o<
~
en
::D
sl>:
Writing to these devices is accomplished when write
enable (WE) and CE1 inputs are both LOW and CE2 is
HIGH. Reading is accomplished when WE and CE2 remain
HIGH and CE1 and OE go LOW. The device offers reduced
power standby modes when disabled. This allows system
designers to meet low standby power requirements.
The "L" and "LP" versions each provide a 70% reduction
in CMOS standby current (ISB2) over the standard version.
The "LP" version also provides a 90% reduction in TTL
standby current (ISB1). This is achieved by including gated
inputs on the WE, OE and address lines. The gated inputs
also facilitate the design of battery backed systems where
the designer needs to protect against inadvertent battery
current drain during power-down, when inputs may be at
undefined levels.
All devices operate from a single +5V power supply and
all inputs and outputs are fully TIL-compatible.
MT5C1008
REV. 12/93
1-161
Micron Semiconductor, Inc., reserves the right to change products or specifications without nolice.
©1993, Micron Semiconductor, Inc.




Micron

MT5C1008 Datasheet Preview

MT5C1008 Datasheet

128K x 8 SRAM

No Preview Available !

U1
FUNCTIONAL BLOCK DIAGRAM
o< Vee GND
Ci
en
:xJ
ls>:
AO-A16
a:
w
aoo
ow
C/)
C/)
w
a:
o
«o
1,048,576-BIT
MEMORY ARRAY
a- l
a:
aoIz-
~
DOS
.__-----' D01
IO--~t-- CE1
I---~ CE2
Io---+--H- OE
'-----.l=~~;- WE
POWER
DOWN f----'
MT5Cl00B
REV. 12/93
TRUTH TABLE
MODE
STANDBY
STANDBY
READ
NOT SELECTED
WRITE
OE CE1 CE2 WE DO
POWER
X H X X HIGH-Z STANDBY
X X L X HIGH-Z STANDBY
L L H H Q ACTIVE
H L H H HIGH-Z ACTIVE
X L H L D ACTIVE
1-162
Micron Semiconductor, Inc., reserves the right to change products or specifications without nOllce
©1993, Micron Semiconductor,lnc


Part Number MT5C1008
Description 128K x 8 SRAM
Maker Micron
PDF Download

MT5C1008 Datasheet PDF






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