QS5930T driver equivalent, low skew cmos pll clock driver.
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* 5V operation Q/2 output, 5 Q outputs Useful for Pentium, PowerPC, and PCI systems Internal .
to be customized for linear VCO operation over a wide range of input SYNC frequencies. The PLL can also be disabled by t.
The QS5930T Clock Driver uses an internal phase locked loop (PLL) to lock low skew outputs to a reference clock input. Six outputs are available: Q0
–Q4, Q/2. Careful layout and design ensure < 250ps skew between the Q0
.
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