Datasheet4U Logo Datasheet4U.com

QS5919T - LOW SKEW TTL PLL CLOCK DRIVER

Description

The QS5919T Clock Driver uses an internal phase locked loop (PLL) to lock low skew outputs to one of two reference clock inputs.

Eight outputs are available: 2xQ, Q 0-Q4, Q5, Q/2.

Careful layout and design ensure < 350ps skew between the Q0-Q4, and Q/2 outputs.

Features

  • 5V operation Low noise TTL level outputs < 350ps output skew, Q0.
  • Q4 2xQ output, Q outputs, Q output, Q/2 output Outputs 3-state and reset while OE/RST low PLL disable feature for low frequency testing Internal loop filter RC network Functional equivalent to Motorola MC88915 Positive or negative edge synchronization (PE) Balanced drive outputs ±24mA 160MHz maximum frequ.

📥 Download Datasheet

Datasheet Details

Part number QS5919T
Manufacturer Integrated Device Technology
File Size 163.47 KB
Description LOW SKEW TTL PLL CLOCK DRIVER
Datasheet download datasheet QS5919T Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
QS5100 Digital FX LSI Altonics
QS518 Solder Profile and Stencil Design Spreadtrum
QS5244 Low Skew CMOS 8 Bit Buffer / Line Drivers Quality
QS54FCT2521T High Speed CMOS 8-Bit Identity Comparator QUALITY
QS54FCT2543T High-Speed CMOS 8-Bit Bus Interface Latch Transceivers Quality Semiconductor

Other Datasheets by Integrated Device Technology

Part Number Description
QS5917T LOW SKEW CMOS PLL CLOCK DRIVER
QS5930T LOW SKEW CMOS PLL CLOCK DRIVER
QS532805 GUARANTEED LOW SKEW 3.3V CMOS CLOCK DRIVER/BUFFER
QS532805A GUARANTEED LOW SKEW 3.3V CMOS CLOCK DRIVER/BUFFER
QS532805B GUARANTEED LOW SKEW 3.3V CMOS CLOCK DRIVER/BUFFER

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
www.DataSheet.co.kr QS5919T LOW SKEW TTL PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER INDUSTRIAL TEMPERATURE RANGE LOW SKEW TTL PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER FEATURES: • • • • • • • • • • • • 5V operation Low noise TTL level outputs < 350ps output skew, Q0–Q4 2xQ output, Q outputs, Q output, Q/2 output Outputs 3-state and reset while OE/RST low PLL disable feature for low frequency testing Internal loop filter RC network Functional equivalent to Motorola MC88915 Positive or negative edge synchronization (PE) Balanced drive outputs ±24mA 160MHz maximum frequency (2xQ output) Available in QSOP and PLCC packages QS5919T DESCRIPTION The QS5919T Clock Driver uses an internal phase locked loop (PLL) to lock low skew outputs to one of two reference clock inputs.
Published: |