QS5919T driver equivalent, low skew ttl pll clock driver.
*
*
*
*
*
*
*
*
*
*
*
* 5V operation Low noise TTL level outputs < 350ps output skew, Q0
–Q4 2xQ output, Q.
to be customized for linear VCO operation over a wide range of input SYNC frequencies. The PLL can also be disabled by t.
The QS5919T Clock Driver uses an internal phase locked loop (PLL) to lock low skew outputs to one of two reference clock inputs. Eight outputs are available: 2xQ, Q 0-Q4, Q5, Q/2. Careful layout and design ensure < 350ps skew between the Q0-Q4, and Q.
Image gallery
TAGS
Download (Size : 163.47KB)