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QS532805A - GUARANTEED LOW SKEW 3.3V CMOS CLOCK DRIVER/BUFFER

This page provides the datasheet information for the QS532805A, a member of the QS532805 GUARANTEED LOW SKEW 3.3V CMOS CLOCK DRIVER/BUFFER family.

Description

The QS532805 clock buffer/driver circuits can be used for clock buffering schemes where low skew is a key parameter.

This device offers two banks of 5 non-inverting outputs.

The QS532805 incorporates 25 Ω series termination resistors.

Features

  • JEDEC compatible LVTTL level inputs and outputs 10 output, low skew clock signal buffer Monitor output Clock inputs are 5V tolerant Pinout and function compatible with QS5805T 25Ω on-chip resistors for low noise Input hysteresis for better noise margin Guaranteed low skew:.
  • 0.7ns output skew.
  • 0.7ns pulse skew.
  • 1ns part-to-part skew Std. , A, and B speed grades (B speed in QSOP package only).

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Datasheet Details

Part number QS532805A
Manufacturer Integrated Device Technology
File Size 109.30 KB
Description GUARANTEED LOW SKEW 3.3V CMOS CLOCK DRIVER/BUFFER
Datasheet download datasheet QS532805A Datasheet
Additional preview pages of the QS532805A datasheet.

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Full PDF Text Transcription

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QS532805/A/B GUARANTEED LOW SKEW 3.3V CMOS CLOCK DRIVER/BUFFER INDUSTRIAL TEMPERATURE RANGE GUARANTEED LOW SKEW 3.3V CMOS CLOCK DRIVER/BUFFER FEATURES: − − − − − − − − JEDEC compatible LVTTL level inputs and outputs 10 output, low skew clock signal buffer Monitor output Clock inputs are 5V tolerant Pinout and function compatible with QS5805T 25Ω on-chip resistors for low noise Input hysteresis for better noise margin Guaranteed low skew: • 0.7ns output skew • 0.7ns pulse skew • 1ns part-to-part skew Std., A, and B speed grades (B speed in QSOP package only) Available in QSOP and SOIC packages QS532805/A/B DESCRIPTION The QS532805 clock buffer/driver circuits can be used for clock buffering schemes where low skew is a key parameter.
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