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QS5930T - LOW SKEW CMOS PLL CLOCK DRIVER

General Description

The QS5930T Clock Driver uses an internal phase locked loop (PLL) to lock low skew outputs to a reference clock input.

Q4, Q/2.

Q4, and Q/2 outputs.

Key Features

  • 5V operation Q/2 output, 5 Q outputs Useful for Pentium, PowerPC, and PCI systems Internal loop filter RC network Low noise TTL level outputs 2000V Latch up > -30.

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Datasheet Details

Part number QS5930T
Manufacturer Integrated Device Technology
File Size 117.22 KB
Description LOW SKEW CMOS PLL CLOCK DRIVER
Datasheet download datasheet QS5930T Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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www.DataSheet.co.kr QS5930T LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER INDUSTRIAL TEMPERATURE RANGE LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER FEATURES: • • • • • • • • • • • • • 5V operation Q/2 output, 5 Q outputs Useful for Pentium, PowerPC, and PCI systems Internal loop filter RC network Low noise TTL level outputs <250ps rising edge output skew Balanced drive outputs ±24mA PLL bypass feature for low frequency testing Internal VCO/2 option for wider frequency range Outputs tri-state and reset while OE/RST is low ESD > 2000V Latch up > -300mA Available in QSOP package QS5930T DESCRIPTION The QS5930T Clock Driver uses an internal phase locked loop (PLL) to lock low skew outputs to a reference clock input. Six outputs are available: Q0–Q4, Q/2.