M53D5121632A sdram equivalent, mobile ddr sdram.
* JEDEC Standard
* Internal pipelined double-data-rate architecture, two data
access per clock cycle
* Bi-directional data strobe (DQS)
* No DLL; CLK to D.
Ball Name
Function
A0~A12, BA0~BA1
Address inputs - Row address A0~A12 - Column address A0~A9 A10/AP : AUTO Precharge BA0~BA1 : Bank selects (4 Banks)
DQ0~DQ15 Data-in/Data-out
RAS CAS WE VSS VDD
LDQS, UDQS
Row address strobe
Column address st.
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