M53D256328A sdram equivalent, lpddr sdram.
* JEDEC Standard
* Internal pipelined double-data-rate architecture, two data
access per clock cycle
* Bi-directional data strobe (DQS)
* No DLL; CLK to D.
Ball Name
Function
A0~A11, BA0~BA1
Address inputs - Row address A0~A11 - Column address A0~A8 A10/AP : AUTO Precharge BA0~BA1: Bank selects (4 Banks)
DQ0~DQ31 Data-in/Data-out
RAS CAS WE VSS VDD
DQS0~DQS3
Row address strobe
Column address stro.
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