JEDEC Standard Internal pipelined double-data-rate architecture, two data access per clock cycle Bi-directional data strobe (DQS) No DLL; CLK to DQS is not synchronized. .

M53D128324A

M53D1G1664A

M53D1G3232A

M53D2561616A

M53D256328A

M53D5121632A

M53D5123216A

M53D64164A

M53

M5300

M5301

M5302

M5303

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