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Cypress Semiconductor Electronic Components Datasheet

CY7C1338F Datasheet

4-Mb (128K x 32) Flow-Through Sync SRAM

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CY7C1338F
4-Mb (128K x 32) Flow-Through Sync SRAM
Features
• 128K X 32 common I/O
• 3.3V –5% and +10% core power supply (VDD)
• 2.5V or 3.3V I/O supply (VDDQ)
• Fast clock-to-output times
— 6.5 ns (133-MHz version)
— 7.5 ns (117-MHz version)
— 8.0 ns (100-MHz version)
— 11.0 ns (66-MHz version)
• Provide high-performance 2-1-1-1 access rate
User-selectable burst counter supporting Intel
Pentiuminterleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed write
• Asynchronous output enable
• Offered in JEDEC-standard 100-pin TQFP and 119-ball
BGA packages
• “ZZ” Sleep Mode option
Functional Description[1]
The CY7C1338F is a 131,072 x 32 synchronous cache RAM
designed to interface with high-speed microprocessors with
minimum glue logic. Maximum access delay from clock rise is
Logic Block Diagram
A0, A1, A
MODE
ADV
CLK
ADDRESS
REGISTER
A[1:0]
BURST Q1
COUNTER
AND LOGIC
CLR Q0
ADSC
ADSP
BWD
DQD BYTE
WRITE REGISTER
6.5 ns (133-MHz version). A 2-bit on-chip counter captures the
first address in a burst and increments the address automati-
cally for the rest of the burst access. All synchronous inputs
are gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CCoEn1tr)o, ldeinppthu-tesxp(AanDsSioCn,
Chip Enables
ADSP, and
(CE2
ADV),
aWndriCteE3E),naBbulresst
(BW[A:D], and
inputs include
BWE), and Global
the Output Enable
(WOErit)ea(nGdWth)e.
Asynchronous
ZZ pin.
The CY7C1338F allows either interleaved or linear burst
sequences, selected by the MODE input pin. A HIGH selects
an interleaved burst sequence, while a LOW selects a linear
burst sequence. Burst accesses can be initiated with the
Processor Address Strobe (ADSP) or the cache Controller
Address Strobe (ADSC) inputs. Address advancement is
controlled by the Address Advancement (ADV) input.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
The CY7C1338F operates from a +3.3V core power supply
while all outputs may operate with either a +2.5 or +3.3V
supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
DQD BYTE
WRITE REGISTER
BWC
BWB
BWA
BWE
GW
CE1
CE2
CE3
OE
DQC BYTE
WRITE REGISTER
DQB BYTE
WRITE REGISTER
DQA BYTE
WRITE REGISTER
ENABLE
REGISTER
DQC BYTE
WRITE REGISTER
DQB BYTE
WRITE REGISTER
DQA BYTE
WRITE REGISTER
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
BUFFERS
DQs
INPUT
REGISTERS
ZZ
SLEEP
CONTROL
Note:
1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-05218 Rev. *A
Revised February 2, 2004


Cypress Semiconductor Electronic Components Datasheet

CY7C1338F Datasheet

4-Mb (128K x 32) Flow-Through Sync SRAM

No Preview Available !

Selection Guide
133 MHz
117 MHz
Maximum Access Time
6.5 7.5
Maximum Operating Current
225 220
Maximum Standby Current
40 40
Shaded areas contain advance information.
Please contact your local Cypress sales representative for availablity of these parts.
Pin Configurations
100-Pin TQFP
100 MHz
8.0
205
40
CY7C1338F
66 MHz
11.0
195
40
Unit
ns
mA
mA
BYTE C
BYTE D
NC
DQC
DQC
VDDQ
VSSQ
DQC
DQC
DQC
DQC
VSSQ
VDDQ
DQC
DQC
NC
VDD
NC
VSS
DQD
DQD
VDDQ
VSSQ
DQD
DQD
DQD
DQD
VSSQ
VDDQ
DQD
DQD
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1338F
80 NC
79 DQB
78 DQB
77 VDDQ
76 VSSQ
75 DQB
74 DQB
73 DQB
72 DQB
71 VSSQ
70 VDDQ
69 DQB
68 DQB
67 VSS
66 NC
65 VDD
64 ZZ
63 DQA
62 DQA
61 VDDQ
60 VSSQ
59 DQA
58 DQA
57 DQA
56 DQA
55 VSSQ
54 VDDQ
53 DQA
52 DQA
51 NC
BYTE B
BYTE A
Document #: 38-05218 Rev. *A
Page 2 of 17


Part Number CY7C1338F
Description 4-Mb (128K x 32) Flow-Through Sync SRAM
Maker Cypress Semiconductor
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CY7C1338F Datasheet PDF






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