CY7C1329H - 2-Mbit Pipelined Sync SRAM

Cypress Semiconductor

📥 Download Datasheet

CY7C1329H Datasheet Preview — Preview of CY7C1329H PDF

Datasheet Details

Part number	CY7C1329H
Manufacturer	Cypress Semiconductor
File Size	435.93 KB
Description	2-Mbit Pipelined Sync SRAM
Datasheet	CY7C1329H-CypressSemiconductor.pdf

CY7C1329H Product details

Description

The CY7C1329H SRAM integrates 64 K × 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation.All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK).The synchronous inputs include all add

Features

Registered inputs and outputs for pipelined operation.
64 K × 32 common I/O architecture.
3.3 V core power supply.
2.5 V/3.3 V I/O operation.
Fast clock-to-output times.
4.0 ns (for 133-MHz device).
Provide high-performance 3-1-1-1 access rate.
User-selectable burst counter supporting Intel Pentium® interleaved or linear burst sequences.
Separate processor and controller address strobes.
Synchronous self-timed write.
Asynchronous output e.

📁 CY7C1329H Similar Datasheet

CY7C131AE - 1K/2K x 8 Dual-Port Static RAM (Cypress)
CY7C131E - 1K/2K x 8 Dual-Port Static RAM (Cypress)
CY7C136AE - 1K/2K x 8 Dual-Port Static RAM (Cypress)
CY7C136E - 1K/2K x 8 Dual-Port Static RAM (Cypress)
CY7C1370C - 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture (Cypress)
CY7C1370CV25 - 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture (Cypress)
CY7C1370D - 18-Mbit (512 K 횞 36/1 M 횞 18) Pipelined SRAM (Cypress)
CY7C1371C - 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL Architecture (Cypress)

Other Datasheets by Cypress Semiconductor

CY7C1329 - 64K x 32 Synchronous-Pipelined Cache RAM
CY7C132 - 2K x 8 Dual-Port Static RAM
CY7C1320AV18 - 18-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1320BV18 - 18-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1320CV18 - (CY7C1xxxCV18) 18-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1320JV18 - 18-Mbit DDR-II SRAM 2-Word Burst Architecture

Published: Mar 13, 2017 |