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CY7C1329H - 2-Mbit Pipelined Sync SRAM

Description

for internal burst operation.

All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK).

Features

  • Registered inputs and outputs for pipelined operation.
  • 64 K × 32 common I/O architecture.
  • 3.3 V core power supply.
  • 2.5 V/3.3 V I/O operation.
  • Fast clock-to-output times.
  • 4.0 ns (for 133-MHz device).
  • Provide high-performance 3-1-1-1 access rate.
  • User-selectable burst counter supporting Intel Pentium® interleaved or linear burst sequences.
  • Separate processor and controller address strobes.
  • Synchronous self-timed write.
  • Asynchronous output e.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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CY7C1329H 2-Mbit (64 K × 32) Pipelined Sync SRAM 2-Mbit (64 K × 32) Pipelined Sync SRAM Features ■ Registered inputs and outputs for pipelined operation ■ 64 K × 32 common I/O architecture ■ 3.3 V core power supply ■ 2.5 V/3.3 V I/O operation ■ Fast clock-to-output times ❐ 4.
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