Datasheet Summary
2-Mbit (64 K × 32) Pipelined Sync SRAM
2-Mbit (64 K × 32) Pipelined Sync SRAM
Features
- Registered inputs and outputs for pipelined operation
- 64 K × 32 mon I/O architecture
- 3.3 V core power supply
- 2.5 V/3.3 V I/O operation
- Fast clock-to-output times
- 4.0 ns (for 133-MHz device)
- Provide high-performance 3-1-1-1 access rate
- User-selectable burst counter supporting Intel Pentium® interleaved or linear burst sequences
- Separate processor and controller address strobes
- Synchronous self-timed write
- Asynchronous output enable
- Offered in JEDEC-standard lead-free 100-pin TQFP package
- “ZZ” Sleep Mode Option
Functional Description
The CY7C1329H SRAM integrates...