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Cypress Semiconductor Electronic Components Datasheet

CY7C1323BV25 Datasheet

18-Mbit 4-Word Burst SRAM

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CY7C1323BV25
18-Mbit 4-Word Burst SRAM with DDR-I
Architecture
Features
Functional Description
• 18-Mbit Density (512 Kbit x 36)
• 167-MHz Clock for high bandwidth
• 4-Word Burst for reducing address bus frequency
• Double Data Rate (DDR) interfaces (data transferred at
333 MHz @ 167 MHz)
• Two input clocks (K and K) for precise DDR timing
SRAM uses rising edges only
• Two input clocks for output data (C and C) to minimize
clock-skew and flight-time mismatches.
• Separate Port Selects for depth expansion
• Synchronous internally self-timed writes
• 2.5V core power supply with HSTL Inputs and Outputs
• Available in 165-ball FBGA package (13 x 15 x 1.4 mm)
• Variable drive HSTL output buffers
• Expanded HSTL output voltage (1.4V–1.9V)
• JTAG 1149.1 compatible test access port
Configuration
CY7C1323BV25 - 256K x 36
The CY7C1323BV25 is a 2.5V Synchronous Pipelined SRAM
equipped with DDR-I (Double Data Rate) architecture. The
DDR-I architecture consists of an SRAM core with advanced
synchronous peripheral circuitry and a 2-bit burst counter.
Addresses for Read and Write are latched on alternate rising
edges of the input (K) clock. Write data is registered on the
rising edges of both K and K. Read data is driven on the rising
edges of C and C if provided, or on the rising edge of K and K
if C/C are not provided. Every read or write operation is
associated with four words that burst sequentially into or out
of the device. The burst counter takes in the least two signif-
icant bits of the external address and bursts four 36-bit words.
Depth expansion is accomplished with Port Selects for each
port. Port selects allow each port to operate independently.
Asynchronous inputs include impedance match (ZQ).
Synchronous data outputs (Q, sharing the same physical pins
as the data inputs D) are tightly matched to the two output echo
clocks CQ/CQ, eliminating the need for separately capturing
data from each individual DDR SRAM in the system design.
Output data clocks(C/C) are also provided for maximum
system clocking and data synchronization flexibility.
All synchronous inputs pass through input registers controlled
by the K or K input clocks. All data outputs pass through output
registers controlled by the C or C input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
Logic Block Diagram (CY7C1323BV25)
A(1:0)
Burst
Logic
19 17
A(18:0)
Address
A(18:2) Register
LD
K
K
CLK
Gen.
Vref
R/W
BWS[3:0]
Control
Logic
Write Write Write Write
Reg Reg Reg Reg
512K x 36 Array
Read Data Reg.
144 72
72
Output
Logic
Control
C
C
Reg.
Reg.
Reg.
36
36
36
CQ
CQ
DQ[35:0]
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05631 Rev. *A
Revised April 3, 2006


Cypress Semiconductor Electronic Components Datasheet

CY7C1323BV25 Datasheet

18-Mbit 4-Word Burst SRAM

No Preview Available !

CY7C1323BV25
Selection Guide
Maximum Operating Frequency
Maximum Operating Current
167 MHz
167
700
Pin Configuration
165-ball FBGA (13 x 15 x 1.4 mm) Pinout
CY7C1323BV25 (256K × 36)
1234 5678
A
CQ GND/144M NC/36M R/W BWS2
K
BWS1
LD
B
NC DQ27 DQ18
A
BWS3 K BWS0 A
C NC NC DQ28 VSS A A0 A1 VSS
D NC DQ29 DQ19 VSS VSS VSS VSS VSS
E NC NC DQ20 VDDQ VSS VSS VSS VDDQ
F NC DQ30 DQ21 VDDQ VDD VSS VDD VDDQ
G NC DQ31 DQ22 VDDQ VDD VSS VDD VDDQ
H NC VREF VDDQ VDDQ VDD VSS VDD VDDQ
J NC NC DQ32 VDDQ VDD VSS VDD VDDQ
K NC NC DQ23 VDDQ VDD VSS VDD VDDQ
L NC DQ33 DQ24 VDDQ VSS VSS VSS VDDQ
M NC NC DQ34 VSS VSS VSS VSS VSS
N NC DQ35 DQ25 VSS
A
A
A VSS
P
NC
NC DQ26
A
ACAA
R TDO TCK
A
A
ACAA
Unit
MHz
mA
9
A
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
A
10
GND/72M
NC
DQ17
NC
DQ15
NC
NC
VREF
DQ13
DQ12
NC
DQ11
NC
DQ9
TMS
11
CQ
DQ8
DQ7
DQ16
DQ6
DQ5
DQ14
ZQ
DQ4
DQ3
DQ2
DQ1
DQ10
DQ0
TDI
Pin Definitions
Name
DQ[35:0]
I/O
Input/Output-
Synchronous
LD
BWS0, BWS1,
BWS2, BWS3
Input-
Synchronous
Input-
Synchronous
A, A0, A1
R/W
Input-
Synchronous
Input-
Synchronous
Description
Data Input/Output signals. Inputs are sampled on the rising edge of K and K clocks
during valid write operations. These pins drive out the requested data during a Read
operation. Valid data is driven out on the rising edge of both the C and C clocks during
Read operations or K and K when in single clock mode. When Read access is deselected,
Q[35:0] are automatically three-stated.
Synchronous Load. This input is brought LOW when a bus cycle sequence is to be
defined. This definition includes address and read/write direction. All transactions
operate on a burst of 4 data (two clock periods of bus activity).
Byte Write Select 0, 1, 2 and 3 active LOW. Sampled on the rising edge of the K and
K clocks during Write operations. Used to select which byte is written into the device
during the current portion of the Write operations. Bytes not written remain unaltered.
CY7C1323BV25 BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18]
and BWS3 controls D[35:27]
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte
Write Select will cause the corresponding byte of data to be ignored and not written into
the device.
Address inputs. These address inputs are multiplexed for both Read and Write opera-
tions. A0 and A1 are the inputs to the burst counter. These are incremented in a linear
fashion internally. 19 address inputs are needed to access the entire memory array.
All the address inputs are ignored when the part is deselected.
Synchronous Read/Write Input. When LD is LOW, this input designates the access
type (Read when R/W is HIGH, Write when R/W is LOW) for loaded address. R/W must
meet the set-up and hold times around edge of K.
Document #: 38-05631 Rev. *A
Page 2 of 18


Part Number CY7C1323BV25
Description 18-Mbit 4-Word Burst SRAM
Maker Cypress Semiconductor
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