CY7C1320BV18 architecture equivalent, 18-mbit ddr-ii sram 2-word burst architecture.
* 18-Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36)
* 300-MHz clock for high bandwidth
* 2-Word burst for reducing address bus frequency
* Double Data .
The CY7C1316BV18, CY7C1916BV18, CY7C1318BV18, and CY7C1320BV18 are 1.8V Synchronous Pipelined SRAM equipped with DDR-II architecture. The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter. Addres.
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