CY7C1321KV18 architecture equivalent, 18-mbit ddr ii sram four-word burst architecture.
* 18-Mbit density (1M × 18, 512K × 36)
* 333-MHz clock for high bandwidth
* Four-word burst for reducing address bus frequency
* Double data rate (DDR) in.
CY7C1319KV18 and CY7C1321KV18 are 1.8 V Synchronous Pipelined SRAMs equipped with DDR II architecture. The DDR II consists of an SRAM core with advanced synchronous peripheral circuitry and a two-bit burst counter. Addresses for read and write are la.
Image gallery
TAGS
Manufacturer
Related datasheet
Download (Size : 816.04KB)