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CY7C1321KV18 - 18-Mbit DDR II SRAM Four-Word Burst Architecture

Download the CY7C1321KV18 datasheet PDF. This datasheet also covers the CY7C1319KV18 variant, as both devices belong to the same 18-mbit ddr ii sram four-word burst architecture family and are provided as variant models within a single manufacturer datasheet.

Description

CY7C1319KV18 and CY7C1321KV18 are 1.8 V Synchronous Pipelined SRAMs equipped with DDR II architecture.

The DDR II consists of an SRAM core with advanced synchronous peripheral circuitry and a two-bit burst counter.

Features

  • 18-Mbit density (1M × 18, 512K × 36).
  • 333-MHz clock for high bandwidth.
  • Four-word burst for reducing address bus frequency.
  • Double data rate (DDR) interfaces (data transferred at 666 MHz) at 333 MHz.
  • Two input clocks (K and K) for precise DDR timing.
  • SRAM uses rising edges only.
  • Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches.
  • Echo clocks (CQ and CQ) simplify data capture in high speed systems.
  • Synchronous.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CY7C1319KV18-CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by Cypress (Infineon)

Part Number Description
CY7C1321BV18 1.8V Synchronous Pipelined SRAM
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CY7C1320BV18 18-Mbit DDR-II SRAM 2-Word Burst Architecture
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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
CY7C1319KV18/CY7C1321KV18 18-Mbit DDR II SRAM Four-Word Burst Architecture 18-Mbit DDR II SRAM Four-Word Burst Architecture Features ■ 18-Mbit density (1M × 18, 512K × 36) ■ 333-MHz clock for high bandwidth ■ Four-word burst for reducing address bus frequency ■ Double data rate (DDR) interfaces (data transferred at 666 MHz) at 333 MHz ■ Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only ■ Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches ■ Echo clocks (CQ and CQ) simplify data capture in high speed systems ■ Synchronous internally self-timed writes ■ DDR II operates with 1.5 cycle read latency when DOFF is asserted HIGH ■ Operates similar to DDR I device with one cycle read latency when DOFF is asserted LOW ■ 1.
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