CY7C1320KV18
Features
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- Configurations
CY7C1316KV18
- 2 M × 8 CY7C1916KV18
- 2 M × 9 CY7C1318KV18
- 1 M × 18 CY7C1320KV18
- 512 K × 36
18-Mbit density (2 M × 8, 2 M × 9, 1 M × 18, 512 K × 36) 333-MHz clock for high bandwidth Two-word burst for reducing address bus frequency Double data rate (DDR) interfaces (data transferred at 666 MHz) at 333 MHz Two input clocks (K and K) for precise DDR timing
- SRAM uses rising edges only Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches Echo clocks (CQ and CQ) simplify data capture in high-speed systems Synchronous internally self-timed writes DDR II operates with 1.5 cycle read latency when DOFF is asserted HIGH Operates similar to DDR-I device with 1 cycle read latency when DOFF is asserted LOW 1.8 V core power supply with HSTL inputs and outputs Variable drive HSTL output buffers Expanded HSTL output voltage (1.4 V- VDD)
- Supports both 1.5 V and 1.8 V I/O supply Available in 165-ball FBGA package (13 ×...
