Download CY7C1320CV18 Datasheet PDF
CY7C1320CV18 page 2
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CY7C1320CV18 Key Features

  • 2M x 8 CY7C1916CV18
  • 2M x 9 CY7C1318CV18
  • 1M x 18 CY7C1320CV18

CY7C1320CV18 Description

The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a one-bit burst counter. Addresses for read and write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K.