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CY7C1307BV25 Datasheet 18-Mbit Burst of 4 Pipelined SRAM

Manufacturer: Cypress (now Infineon)

Download the CY7C1307BV25 datasheet PDF. This datasheet also includes the CY7C1305BV25 variant, as both parts are published together in a single manufacturer document.

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Note: The manufacturer provides a single datasheet file (CY7C1305BV25-CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

General Description

• Separate independent Read and Write data ports • Supports concurrent transactions • 167-MHz clock for high bandwidth • 2.5 ns Clock-to-Valid access time • 4-Word Burst for reducing the address bus frequency • Double Data Rate (DDR) interfaces on both Read and Write Ports (data transferred at 333 MHz) @167 MHz • Two input clocks (K and K) for precise DDR timing • SRAM uses rising edges only • Two input clocks for output data (C and C) to minimize clock-skew and flight-time mismatches.

• Single multiplexed address input bus latches address inputs for both Read and Write ports • Separate Port Selects for depth expansion • Synchronous internally self-timed writes • 2.5V core power supply with HSTL Inputs and Outputs • Available in 165-ball FBGA package (13 x 15 x 1.4 mm) • Variable drive HSTL output buffers • Expanded HSTL output voltage

Overview

CY7C1305BV25 CY7C1307BV25 18-Mbit Burst of 4 Pipelined SRAM with QDR™.

Key Features

  • Functional.

More Datasheets from Cypress (now Infineon)

Part Number Description
CY7C1307BV18 18-Mbit Burst of 4 Pipelined SRAM
CY7C130 1K x 8 Dual-Port Static RAM
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CY7C1302DV25 9-Mbit Burst of Two Pipelined SRAMs
CY7C1303BV18 18-Mbit Burst of 2 Pipelined SRAM
CY7C1303BV25 18-Mbit Burst of Two-Pipelined SRAM
CY7C1304DV25 9-Mbit Burst of 4 Pipelined SRAM
CY7C1305BV18 18-Mbit Burst of 4 Pipelined SRAM
CY7C1305BV25 18-Mbit Burst of 4 Pipelined SRAM
CY7C1306BV18 18-Mbit Burst of 2 Pipelined SRAM