CY2SSTV16857 datasheet, buffer equivalent, Cypress Semiconductor

Features and benefits

* Differential Clock Inputs up to 280 MHz
* Supports LVTTL switching levels on the RESET pin
* Output drivers have controlled edge rates, so no external resis.

Description

This 14-bit registered buffer is designed specifically for 2.3V to 2.7V VDD operation and is characterized for operation from 0°C to + 85°C. All inputs are compatible with the JEDEC Standard for SSTL_2, except the LVCMOS reset (RESET) input. All outp.

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