CY7C131E/CY7C131AE
CY7C136E/CY7C136AE
1K/2K × 8 Dual-Port Static RAM
1K/2K × 8 Dual-Port Static RAM
Features
■ True dual-ported memory cells, which allow simultaneous
reads of the same memory location
■ 1K/2K × 8 organization
■ 0.35 micron complementary metal oxide semiconductor
(CMOS) for optimum speed and power
■ High speed access: 15 ns
■ Low operating power: ICC = 110 mA (typical),
Standby: ISB3 = 0.05 mA (typical)
■ Fully asynchronous operation
■ Automatic power-down
■ BUSY output flag to indicate access to the same location by
both ports
■ INT flag for port-to-port communication
■ Available in 52-pin plastic leaded chip carrier (PLCC), 52-pin
plastic quad flat package (PQFP)
■ Pb-free packages available
Functional Description
CY7C131E/CY7C131AE/CY7C136E/CY7C136AE are high-
speed, low-power CMOS 1K/2K × 8 dual-port static RAMs. Two
ports are provided permitting independent access to any location
in memory. The CY7C131E/CY7C131AE/CY7C136E/
CY7C136AE can be used as a standalone dual-port static RAM.
It is the solution to applications requiring shared or buffered data,
such as cache memory for DSP, bit-slice, or multiprocessor
designs.
Each port has independent control pins; chip enable (CE), write
enable (R/W), and output enable (OE). Two flags are provided
on each port, BUSY and INT. The BUSY flag signals that the port
is trying to access the same location, which is currently being
accessed by the other port. The INT is an interrupt flag indicating
that data is placed in a unique location[1]. The BUSY and INT
flags are push pull outputs. An automatic power-down feature is
controlled independently on each port by the chip enable (CE)
pins.
The CY7C131E/CY7C131AE/CY7C136E/CY7C136AE are
available in 52-pin Pb-free PLCC and 52-pin Pb-free PQFP.
For a complete list of related documentation, click here.
Logic Block Diagram
R/WL
CEL
OEL
I/O7L
I/O0L
BUSYL[2]
A 9/10L
[4]
A 0L
I/O
CONTROL
I/O
CONTROL
ADDR
DECODER
MEMORY
ARRAY
ADDR
DECODER
R/WR
CER
OER
I/O7R
I/O0R
BUSYR[2]
A 9/10R
[4]
A 0R
[3]
INTL
CEL
OEL
R/WL
77CCA11R331B6LEEIOT//77RGCCAI1C1T33I1O6AANEE/
A(7RCB1IT3R0/A7TCI1O3N1 LOONGLIYC)
AND
ININTTEERRRRUUPPTTLLOOGGIICC
CER
OER
R/WR
INTR[3]
Notes
1. Unique location used by interrupt flag: 1K × 8: Left port reads from 3FE, Right port reads from 3FF; 2K × 8: Left port reads from 7FE, Right port reads from 7FF.
2. BUSY is a push-pull output. No pull-up resistor required.
3. INT: push-pull output. No pull-up resistor required.
4. 1K × 8: A0–A9, 2K × 8: A0–A10, address lines are for both left and right ports.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-64231 Rev. *J
• San Jose, CA 95134-1709 • 408-943-2600
Revised July 31, 2018
