Cypress Semiconductor CY7 Datasheet | Specifications & PDF Download

36-Mbit QDR II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) 36-Mbit QDR® II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) CY7C

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CY7C1241V18 CY7C1256V18 CY7C1243V18 CY7C1245V18 36-Mbit QDR™-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) Features • Separate independ

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36-Mbit QDR II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) 36-Mbit QDR® II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) CY7C

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36-Mbit QDR II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) 36-Mbit QDR® II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) CY7C

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36-Mbit QDR II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) 36-Mbit QDR® II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) CY7C

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1CY7C1380BV25 PRELIMINARY CY7C1380BV25 CY7C1382BV25 512K x 36 / 1 Mb x 18 Pipelined SRAM Features • • • • • • • • • • • Fast clock speed: 200,166,

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36-Mbit QDR II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) 36-Mbit QDR® II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) CY7C

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36-Mbit QDR II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) 36-Mbit QDR® II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) CY7C

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CY7C1241V18 CY7C1256V18 CY7C1243V18 CY7C1245V18 36-Mbit QDR™-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) Features • Separate independ

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1CY 7C14 0 fax id: 5200 CY7C130/CY7C131 CY7C140/CY7C141 1K x 8 Dual-Port Static Ram Features • True Dual-Ported memory cells which allow simultaneo

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009 CY7C109 CY7C1009 128K x 8 Static RAM Features • High speed — tAA = 10 ns • Low active power — 1017 mW (max., 12 ns) • Low CMOS standby power — 5

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CY7C421512 × 9 Asynchronous FIFO CY7C421 512 × 9 Asynchronous FIFO 512 × 9 Asynchronous FIFO Features ■ Asynchronous First-In First-Out (FIFO) Buffe

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CY7C4425/4205/4215 CY7C4225/4235/4245 64/256/512/1K/2K/4K x 18 Synchronous FIFOs Features ■ High speed, low power, first-in first-out (FIFO) memories

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1CY 7C42 65 fax id: 5413 PRELIMINARY CY7C4255 CY7C4265 8K/16Kx18 Deep Sync FIFOs Features • High-speed, low-power, first-in first-out (FIFO) memor

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CY7C65215 CY7C65215A USB-Serial Dual Channel (UART/I2C/SPI) Bridge with CapSense® and BCD USB-Serial Dual Channel (UART/I2C/SPI) Bridge with CapSense

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CY7C25422KV18 72-Mbit QDR® II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT 72-Mbit QDR® II+ SRAM Two-Word Burst Architecture (

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CY7C2262XV18/CY7C2264XV18 36-Mbit QDR® II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 36-Mbit QDR® II+ Xtreme SRAM Two

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CY7C1010DV33 2-Mbit (256 K × 8) Static RAM 2-Mbit (256 K × 8) Static RAM Features ■ Pin and function compatible with CY7C1010CV33 ■ High speed ❐ tAA

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CY7C1380C CY7C1382C 18-Mb (512K x 36/1M x 18) Pipelined SRAM Features Functional Description[1] • Supports bus operation up to 250 MHz • Available

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CY7C1303BV18 CY7C1306BV18 18-Mbit Burst of 2 Pipelined SRAM with QDR™ Architecture Features Functional Description • Separate independent Read and

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