Datasheet Details
| Part number | ZL30110 |
|---|---|
| Manufacturer | Zarlink Semiconductor |
| File Size | 320.76 KB |
| Description | Telecom Rate Conversion DPLL |
| Datasheet |
 ZL30110 Datasheet
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General Description
The ZL30110 clock rate conversion digital phaselocked loop (DPLL) provides accurate and reliable frequency conversion.
The ZL30110 generates a range of clocks that are either locked to the input reference or locked to the external crystal or oscillator.
Key Features
- Synchronizes to 8 kHz, 2.048 MHz, 8.192 MHz or 16.384 MHz.
- Provides a range of output clocks:.
- 65.536 MHz TDM clock locked to the input reference.
- General purpose 25 MHz fan-out to 6 outputs locked to the external crystal or oscillator.
- General purpose 125 MHz and 66 MHz or 100 MHz locked to the external crystal or oscillator.
- Provides DPLL lock and reference fail indication.
- Automatic free run mode on reference fail.
- DPLL.