Datasheet Details
| Part number | ZL30105 |
|---|---|
| Manufacturer | Zarlink Semiconductor |
| File Size | 613.67 KB |
| Description | T1/E1/SDH Stratum 3 Redundant System Clock Synchronizer |
| Datasheet |
 ZL30105 Datasheet
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General Description
The ZL30105 SDH/PDH System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization for SDH and T1/E1 transmission equipment.
It provides advanced support for systems deploying redundant clocks.
Key Features
- Synchronizes to clock-and-sync-pair to maintain minimal phase skew between the master-clock and the redundant slave-clock.
- Supports ITU-T G.813 option 1, G.823 for 2048 kbit/s and G.824 for 1544 kbit/s interfaces.
- Supports Telcordia GR-1244-CORE Stratum 3/4/4E.
- Supports ANSI T1.403 and ETSI ETS 300 011 for ISDN primary rate interfaces.
- Accepts three input references and synchronizes to any combination of 2 kHz, 8 kHz, 1.544 MHz, 2.048 MHz, 8.192 MHz,.