ST2301
DESCRIPTION
The ST2301 is the P-Channel logic enhancement mode power field effect transistor are produced using high cell density, DMOS trench technology. This high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage application such as cellular phone and notebook puter power management and other batter powered circuits, and low in-line power loss are needed in a very small outine surface mount package.
PIN CONFIGURATION SOT-23-3L 3
FEATURE z -20V/-2.8A, RDS(ON) = 120m-ohm @VGS = -4.5V z -20V/-2.0A, RDS(ON) = 170m-ohm @VGS = -2.5V z Super high density cell design for extremely low RDS(ON) z Exceptional on-resistance and maximum DC current capability z SOT-23-3L package design
1.Gate 2.Source
3.Drain
S: Subcontractor Y: Year Code
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S01YA
A: Process Code ata w.D
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STANSON TECHNOLOGY
120 Bentley Square, Mountain View, Ca 94040 USA TEL: (650) 9389294 FAX: (650)...
