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QL3060 pASIC 3 FPGA Data Sheet
••••••
60,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density
Device Highlights
High Performance & High Density
• 60,000 Usable PLD Gates with 316 I/Os • 300 MHz 16-bit www.DataSheet4U.com
Eight Low-Skew Distributed Networks
• Two array clock/control networks available
Counters, 400 MHz Datapaths • 0.